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CY7C68000
TX2TM USB 2.0 UTMI Transceiver
1.0 EZ-USB TX2TM Features
* Synchronous field and EOP detection on receive packets * Synchronous field and EOP generation on transmit packets * Data and clock recovery from the USB serial stream * Bit stuffing/unstuffing; bit stuff error detection * Staging register to manage data rate variation due to bit stuffing/unstuffing * 16-bit 30-MHz, and 8-bit 60-MHz parallel interface * Ability to switch between FS and HS terminations and signaling * Supports detection of USB reset, suspend, and resume * Supports HS identification and detection as defined by the USB 2.0 Specification * Supports transmission of resume signaling * 3.3 V operation * Two package options--56-pin QFN, and 56-pin SSOP * All required terminations, including 1.5K-ohm pull up on DPLUS, are internal to the chip * Supports USB 2.0 test modes
The Cypress EZ-USB TX2TM is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial/deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The TX2 provides a high-speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex highspeed analog USB components external to the digital ASIC which decreases development time and associated risk. A standard interface is provided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01. Two packages are defined for the family: 56-pin SSOP and 56pin QFN. The function block diagram is shown in Figure 1-1. The features of the EX-USB TX2 are: * UTMI-compliant/USB-2.0-certified for device operation * Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second * Serial-to-parallel and parallel-to-serial conversions * 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface
CY7C68000
CY7C68000
XTALIN/ OUT
OSC
20X PLL
PLL_480
UTMI CLK
UTMI CLK
Full-Speed Rx
High-Speed Rx
USB
USB 2.0 XCVR
Traffic Sync
Elasticity Buffer
Fast Digital Rx Fast Digital Tx
Digital Rx
UTMI Rx Ctl
UTMI Rx Data 8/16
High-Speed Tx
BIDI Option Also
Full-Speed Tx
Digital Tx
UTMI Tx Data 8/16 Rx
UTMI Tx Ctl
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation Document #: 38-08016 Rev. *H
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised May 2, 2006
CY7C68000
2.0
* * * * * * * * * *
Applications
DSL modems ATA interface Memory card readers Legacy conversion devices Cameras Scanners Home PNA Wireless LAN MP3 players Networking
signal. On the CLK edge the state of these lines reflect the state of the USB data lines. Upon the clock edge the 0-bit of the LineState pins is the state of the DPLUS line and the one bit of LineState is the DMINUS line. When synchronized, the set up and hold timing of the LineState is identical to the parallel data bus.
3.6
Full-speed vs. High-speed Select
3.0
3.1
Functional Overview
USB Signaling Speed
The FS vs. HS is done through the use of both XcvrSelect and the TermSelect input signals. The TermSelect signal enables the 1.5 K ohm pull up on to the DPLUS pin. When TermSelect is driven LOW, a SE0 is asserted on the USB providing the HS termination and generating the HS Idle state on the bus. The XcvrSelect signal is the control which selects either the FS transceivers or the HS transceivers. To select the HS transceivers, set this pin to `0'. To select the FS transceivers, set this pin to `1'.
TX2 operates at two of the rates defined in the USB Specification 2.0, dated April 27, 2000: * Full speed, with a signaling bit rate of 12 Mbps * High speed, with a signaling bit rate of 480 Mbps TX2 does not support the low-speed (LS) signaling rate of 1.5 Mbps.
3.7
Operational Modes
The operational modes are controlled by the OpMode signals. The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input. OpMode[1:0] 00 01 10 11 Mode 0 1 2 3 Description Normal operation Non-driving Disable Bit Stuffing and NRZI encoding Reserved
3.2
Transceiver Clock Frequency
TX2 has an on-chip oscillator circuit that uses an external 24MHz (100-ppm) crystal with the following characteristics: * Parallel resonant * Fundamental mode * 500-W drive level * 27-33 pF (5% tolerance) load capacitors An on-chip phase-locked loop (PLL) multiplies the 24-MHz oscillator up to 30/60 MHz, as required by the transceiver parallel data bus. The default UTMI interface clock (CLK) frequency is determined by the DataBus16_8 pin.
Mode 0 allows the transceiver to operate with normal USB data decoding and encoding. Mode 1 allows the transceiver logic to support a soft disconnect feature which three-states both the HS and FS transmitters, and removes any termination from the USB, making it appear to an upstream port that the device has been disconnected from the bus. Mode 2 disables Bit Stuff and NRZI encoding logic so 1s loaded from the data bus becomes Js on the DPLUS/DMINUS lines and 0s become Ks.
3.3
Buses
The two packages allow for 8/16-bit bidirectional data bus for data transfers to a controlling unit.
3.4
Reset Pin
An input pin (Reset) resets the chip. This pin has hysteresis and is active HIGH according to the UTMI specification. The internal PLL stabilizes approximately 200 s after VCC has reached 3.3V.
4.0
DPLUS/DMINUS Impedance Termination
3.5
Line State
The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the J and the K states. They are synchronized to the CLK signal for a valid
The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part.
Document #: 38-08016 Rev. *H
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CY7C68000
5.0 Pin Assignments
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin SSOP packages. The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface. 56-pin QFN
DataBus16_8
Reserved
Uni_bidi
TXValid
ValidH
56
GND
CLK
VCC
55
VCC
D0
D1
D2
D3
D4
54
53
52
51
50
49
48
47
46
45
44
43
TXReady Suspend Reset AVCC XTALOUT XTALIN AGND AVCC DPLUS
1 2 3 4 5 6 7 8 9
42 41 40 39 38 37
GND D5 Reserved D6 D7 D8 D9 Reserved D10 D11 VCC D12 GND D13
CY7C68000
56-pin QFN
36 35 34 33 32 31 30 29
DMINUS 10 AGND
11
XcvrSelect 12 TermSelect 13 OpMode0 14
15 Document #: 38-08016 Rev. *H 16 17 18 19 20 21 22 23 24 25 26 27 28
OpMode1
GND
Figure 5-1. CY7C68000 56-pin QFN Pin Assignment
VCC
LineState0
LineState1
GND
RXValid
RXActive
RXError
Reserved
Reserved
D15
D14
VCC
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CY7C68000
56-pin SSOP
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CLK DataBus16_8 Uni_Bidi GND TXValid VCC ValidH TXReady Suspend Reset AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND XcvrSelect TermSelect OpMode0 OpMode1 GND VCC LineState0 LineState1 GND RXValid
D0 D1 Reserved D2 VCC D3 D4 GND D5 Reserved D6 D7 D8 D9 Reserved D10 D11 VCC D12 GND D13 VCC D14 D15 Reserved Reserved RXError RXActive
Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment
5.1
CY7C68000 Pin Descriptions
Name AVCC AVCC AGND AGND DPLUS DMINUS Type Power Power Power Power I/O/Z I/O/Z Default N/A N/A N/A N/A Z Z Description Analog VCC. This signal provides power to the analog section of the chip. Analog VCC. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. Analog Ground. Connect to ground with as short a path as possible. USB DPLUS Signal. Connect to the USB DPLUS signal. USB DMINUS Signal. Connect to the USB DMINUS signal.
Table 5-1. Pin Descriptions [1] SSOP QFN 11 15 14 18 16 17 4 8 7 11 9 10
Note: 1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby.
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CY7C68000
Table 5-1. Pin Descriptions (continued)[1] SSOP QFN 56 55 53 51 50 48 46 45 44 43 41 40 38 36 34 33 1 10 49 48 46 44 43 41 39 38 37 36 34 33 31 29 27 26 50 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK Reset Name Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Input N/A Clock. This output is used for clocking the receive and transmit parallel data on the D[15:0] bus. Active HIGH Reset. Resets the entire chip. This pin can be tied to VCC through a 0.1 F capacitor and to GND through a 100 K resistor for a 10 msec RC time constant. Transceiver Select. This signal selects between the Full Speed (FS) and the High Speed (HS) transceivers: 0: HS transceiver enabled 1: FS transceiver enabled Termination Select. This signal selects between the between the Full Speed (FS) and the High Speed (HS) terminations: 0: HS termination 1: FS termination Suspend. Places the CY7C68000 in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operations. While suspended, TermSelect must always be in FS mode to ensure that the 1.5 K ohm pull-up on DPLUS remains powered. 0: CY7C68000 circuitry drawing suspend current 1: CY7C68000 circuitry drawing normal current Line State. These signals reflect the current state of the single-ended receivers. They are combinatorial until a "usable" CLK is available then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineState0) and DMINUS (LineState1). D- D+ Description 0 0 0: SE0 0 1 1: `J' State 1 0 2: `K' State 1 1 3: SE1 Line State. These signals reflect the current state of the single-ended receivers. They are combinatorial until a `usable' CLK is available then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineState0) and DMINUS (LineState1). D- D+ Description 00-0: SE0 01-1: `J' State 10-2: `K' State 11-3: SE1. Page 5 of 14 Bidirectional Data Bus. This bidirectional bus is used as the upper eight bits of the data bus when in the 16-bit mode, and not used when in the 8-bit bidirectional mode. Under the 8-bit unidirectional mode these bits are used as outputs for data, selected by the TxValid signal. Default Description Bidirectional Data Bus. This bidirectional bus is used as the entire data bus in the 8-bit bidirectional mode or the least significant eight bits in the 16bit mode or under the 8-bit unidirectional mode these bits are used as inputs for data, selected by the RxValid signal.
19
12
XcvrSelect
Input
N/A
20
13
TermSelect
Input
N/A
9
2
Suspend
Input
N/A
26
19
LineState1
Output
25
18
LineState0
Output
Document #: 38-08016 Rev. *H
CY7C68000
Table 5-1. Pin Descriptions (continued)[1] SSOP QFN 22 15 Name OpMode1 Type Input Default Description Operational Mode. These signals select among various operational modes: 10 Description 00-0: Normal Operation 01-1: Non-driving 10-2: Disable Bit Stuffing and NRZI encoding 11-3: Reserved. Operational Mode. These signals select among various operational modes: 10 Description 00-0: Normal Operation 01-1: Non-driving 10-2: Disable Bit Stuffing and NRZI encoding 11-3: Reserved. Transmit Valid. Indicates that the data bus is valid. The assertion of Transmit Valid initiates SYNC on the USB. The negation of Transmit Valid initiates EOP on the USB. The start of SYNC must be initiated on the USB no less than one or no more that two CLKs after the assertion of TXValid. In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the USB between 8- and 16-bit times after the assertion of TXValid is detected by the Transmit State Machine. In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less than one or more than two CLKs after the assertion of TXValid is detected by the Transmit State Machine. Transmit Data Ready. If TXValid is asserted, the SIE must always have data available for clocking in to the TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000 will load the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE should immediately present the data for the next transfer on the data bus. Receive Data Valid. Indicates that the DataOut bus has valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the DataOut bus on the clock edge. Receive Active. Indicates that the receive state machine has detected SYNC and is active. RXActive is negated after a bit stuff error or an EOP is detected. Receive Error. 0 Indicates no error. 1 Indicates that a receive error has been detected. ValidH. This signal indicates that the high-order eight bits of a 16-bit data word presented on the Data bus are valid. When DataBus16_8 = 1 and TXValid = 0, ValidH is an output, indicating that the high-order receive data byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1, ValidH is an input and indicates that the high-order transmit data byte, presented on the Data bus by the transceiver, is valid. When DataBus16_8 = 0, ValidH is undefined. The status of the receive low-order data byte is determined by RXValid and are present on D0-D7. Data Bus 16_8. Selects between 8- and 16-bit data transfers. 1-16-bit data path operation enabled. CLK = 30 MHz. 0-8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are undefined. When Uni_Bidi =1, D[0:7] are valid on RxValid and D[8:15] are valid on TxValid. CLK = 60 MHz Note: DataBus16_8 is static after Power-on Reset (POR) and is only sampled at the end of Reset.
21
14
OpMode0
Input
5
54
TXValid
Input
8
1
TXReady
Output
28
21
RXValid
Output
29
22
RXActive
Output
30
23
RXError
Output
7
56
ValidH
I/O
2
51
DataBus16_8
Input
Document #: 38-08016 Rev. *H
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CY7C68000
Table 5-1. Pin Descriptions (continued)[1] SSOP QFN 13 6 Name XTALIN Type Input Default N/A Description Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave derived from another clock source. Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and 30-pF (nominal) capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. Driving this pin HIGH enables the unidirectional mode when the 8-bit interface is selected. Uni_Bidi is static after power on reset (POR). VCC. Connect to 3.3V power source. N/A N/A N/A N/A N/A N/A N/A N/A N/A VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. Ground. Ground. Ground. Ground. Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground.
12
5
XTALOUT
Output
N/A
3 6 24 35 39 52 4 23 27 37 49 31 54 47 42 32
52 55 17 28 32 45 53 16 20 30 42 24 47 40 35 25
Uni_Bidi VCC VCC VCC VCC VCC GND GND GND GND GND Reserved Reserved Reserved Reserved Reserved
Input Power Power Power Power Power Ground Ground Ground Ground Ground INPUT INPUT INPUT INPUT INPUT
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CY7C68000
6.0 Absolute Maximum Ratings 7.0 Operating Conditions
Storage Temperature .................................-65C to +150C Ambient Temperature with Power Supplied ...... 0C to +70C Supply Voltage to Ground Potential ............... -0.5V to +4.0V DC Input Voltage to Any Input Pin .............................. 5.25 V DC Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Power Dissipation .....................................................630 mW Static Discharge Voltage ...........................................> 2000V Max Output Current, per IO pin..................................... 4 mA Max Output Current, all 21-IO pins ............................84 mA TA (Ambient Temperature Under Bias) ............. 0C to +70C Supply Voltage................................................+3.0V to +3.6V Ground Voltage.................................................................. 0V FOSC (Oscillator or Crystal Frequency).... 24 MHz 100 ppm ................................................................... Parallel Resonant
8.0
DC Characteristics
Table 8-1. DC Characteristics Parameter VCC VIH VIL II VOH VOL IOH IOL CIN CLOAD ISUSP ICC ICC tRESET Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Voltage High Output Low Voltage Output Current High Output Current Low Input Pin Capacitance Maximum Output Capacitance Suspend Current Supply Current HS Mode Supply Current FS Mode Minimum Reset time Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins Connected[2] Disconnected[2] Normal operation OPMOD[1:0] = 00 Normal operation OPMOD[1:0] = 00 1.9 235 15 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 30 293 55 175 90 Conditions Min. 3.0 2 -0.5 Typ. 3.3 Max. 3.6 5.25 0.8 10 Unit V V V A V V mA mA pF pF pF A A mA mA ms
8.1
USB 2.0 Transceiver
USB 2.0 compliant in FS and HS modes.
Note: 2. Connected to the USB includes 1.5k-ohm internal pull-up. Disconnected has the 1.5k-ohm internal pull-up excluded.
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CY7C68000
9.0
9.1
AC Electrical Characteristics
USB 2.0 Transceiver
USB 2.0 certified in FS and HS.
9.2
9.2.1
Timing Diagram
HS/FS Interface Timing-60 MHz
CLK TCH_MIN TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCCO Control_Out TCDO DataOut
Figure 9-1. 60-MHz Interface Timing Constraints Table 9-1. 60-MHz Interface Timing Constraints Parameters Parameter TCSU_MIN TCH_MIN TDSU_MIN TDH_MIN TCCO TCDO Description Minimum set-up time for TXValid Minimum hold time for TXValid Minimum set-up time for Data (transmit direction) Minimum hold time for Data (transmit direction) Clock to Control out time for TXReady, RXValid, RXActive and RXError Clock to Data out time (Receive direction) Min. 8 1 8 1 1 1 8 8 Typ. Max. Unit ns ns ns ns ns ns Notes
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CY7C68000
9.2.2 HS/FS Interface Timing-30 MHz
CLK TCH_MIN TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCDO TCCO TCVO TVH_MIN TVSU_MIN DataOut
Control_Out
Figure 9-2. 30-MHz Timing Interface Timing Constraints
Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters Parameter TCSU_MIN TCH_MIN TDSU_MIN TDH_MIN TCCO TCDO TVSU_MIN TVH_MIN TCVO Description Minimum set-up time for TXValid Minimum hold time for TXValid Minimum set-up time for Data (Transmit direction) Minimum hold time for Data (Transmit direction) Clock to Control Out time for TXReady, RXValid, RXActive and RXError Clock to Data out time (Receive direction) Minimum set-up time for ValidH (transmit Direction) Minimum hold time for ValidH (Transmit direction) Clock to ValidH out time (Receive direction) Min. 20 1 20 1 1 1 20 1 1 20 20 20 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Notes
Document #: 38-08016 Rev. *H
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CY7C68000
10.0 Ordering Information
Table 10-1. Ordering Information Ordering Code CY7C68000-56LFXC CY7C68000-56LFXCT CY7C68000-56PVC CY7C68000-56PVCT CY7C68000-56PVXC CY7C68000-56PVXCT CY3683 56 QFN (Pb-Free) 56 QFN (Pb-Free) Tap/Reel 56 SSOP 56 SSOP Tape/Reel 56 SSOP (Pb-Free) 56 SSOP (Pb-Free) Tape/Reel EZ-USB TX2 Development Board Package Type
11.0
Package Diagrams
The TX2 is available in two packages: * 56-pin SSOP * 56-pin QFN.
51-85062-*C
Figure 11-1. 56-lead Shrunk Small Outline Package O56
Document #: 38-08016 Rev. *H
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CY7C68000
56-Lead QFN 8 x 8 mm (Sawn Version) LS56B
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 TOP VIEW SIDE VIEW BOTTOM VIEW
0.08[0.003] A PIN #1 CORNER 7.90[0.311] 8.10[0.319] 1.00[0.039] MAX.
C
0.20[0.008] REF. 0.04[0.0015] MAX.
0.18[0.007] 0.28[0.011]
PIN #1 CORNER
7.90[0.311]
8.10[0.319]
E-PAD
(PAD SIZE VARY BY DEVICE TYPE)
0.30[0.012] 0.50[0.020]
C
0.50[0.020] SEATING PLANE 6.45[0.254] 6.55[0.258]
E-PAD maximum size 4.75 X 5.46 mm [187 x 215 mils] (width x length).
51-85187-*A
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)
12.0
PCB Layout Recommendations[3]
* Bypass/flyback capacitors on VBus, near the connector, are recommended. * DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm. * Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. * If possible, do not place any vias on the DPLUS or DMINUS trace routing. * Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.
The following recommendations should be followed to ensure reliable high-performance operation. * At least a four-layer impedance controlled boards are required to maintain signal quality. * Specify impedance targets (ask your board vendor what they can achieve). * To control impedance, maintain trace widths and trace spacing to within specifications. * Minimize stubs to minimize reflected signals. * Connections between the USB connector shell and signal ground must be done near the USB connector.
Note: 3. Source for recommendations: EZ-USB FX2TM PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf HighSpeed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
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6.45[0.254] 6.55[0.258]
CY7C68000
13.0 Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the TX2 through the device's metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by an array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note "Surface Mount Assembly of AMKOR's MicroLeadFrame (MLF) Technology." This application note can be downloaded from AMKOR's web site from the following URL http://www.amkor.com/products/notes_papers/MLFApp Note.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 13-1 below displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. Cypress recommends that 'No Clean', type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.
0.017" dia Solder Mask Cu Fill Cu Fill
PCB Material
0.013" dia
PCB Material
Via hole for thermally connecting the QFN to the circuit board ground plane.
This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane
Figure 13-1. Crosssection of the Area Underneath the QFN Package Figure 13-2 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).
Figure 13-2. Plot of the Solder Mask (White Area) EZ-USB TX2 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08016 Rev. *H
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C68000
Document History Page
Document Title: CY7C68000 TX2TM USB 2.0 UTMI Transceiver Document Number: 38-08016 REV. ** *A *B ECN NO. 112019 113885 118521 Issue Date 03/01/02 07/01/02 11/18/02 Orig. of Change KKU KKU KKU/ BHA BHA KKU KKU KKU KKU TEH New data sheet Updated pinouts on BGA package, signal names. Added timing diagrams. Added USB Logo. Updated characterization data. Changed from Preliminary to Final. Changed ISB Suspend Current maximums. Removed BGA package and added Rev C of QFN package drawing with PCB layout Recommendations for the QFN package. Updated description on signals DataBus16_8, and D0-D15. Updated data sheet format. Removed Preliminary and changed block diagram on input to Digital Tx block; was "UTMI Rx Data 8/16" changed to "UTMI Tx Data 8/16" Added note to figure 11-2: E-PAD maximum size 4.75 X 5.46 mm [187 x 215 mils] (width x length). Updated Ordering information to include Pb-Free part numbers. Description of Change
*C *D *E *F *G *H
124507 126665 285634 301832 375694 448451
02/21/03 07/03/03 SEE ECN SEE ECN SEE ECN SEE ECN
Document #: 38-08016 Rev. *H
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